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SoC Canvas Demo – 5. Constraint Generation (SDC)

SoCCanvasFifthDemo – Constraint Generation (SDC)

Constraint는 스크립트가 아니라 설계 의도입니다.

🧭 How to design SoC with SoC Canvas

Episode 5에서는
Clock 구조로부터 SDC를 생성하는 과정을 보여드립니다.
Clock Diagram을 그대로 렌더링하여 SDC 선언을 추가할 수 있습니다.
✔️ create_clock, create_generated_clock
✔️ Clock Group
✔️ Exception

설계와 SDC가 분리되지 않으며,
설계 변경 사항은 SDC에도 실시간으로 반영됩니다.

🎥 Episode 5: Constraint Generation (SDC)
▶️ 전체 데모 영상이 궁금하신 분들은 댓글이나 DM 주시면 링크를 공유해드리겠습니다.


 SoCCanvasFifthDemo  – Constraint Generation (SDC)

Constraints are design intents, not scripts.

🧭 How to design SoC with SoC Canvas

In Episode 5,
we show how to generate SDC directly from your Clock structure.

By rendering the Clock Diagram as-is, you can layer in SDC declarations right on top.
✔️ create_clock, create_generated_clock
✔️ Clock Group
✔️ Exception

The design and the SDC are not separated,
and design changes are reflected in the SDC in real time.

🎥 Episode 5: Constraint Generation (SDC)
▶️ If you are interested in the full demo video, please leave a comment or send a DM, and we will share the link.

💡 Summary
In this video, we explore the SDC (Synopsys Design Constraint) feature of SoC Canvas, designed to simplify the generation of complex timing constraints once the clock design is complete.

SoC Canvas automatically converts the CMU (Clock Management Unit) structure into an SDC-oriented view, enabling engineers to generate Tcl-based constraints such as:

– create_clock
– create_generated_clock

By selecting declaration points directly from the diagram.

This “One Data” approach keeps RTL, timing, and physical design information synchronized in real time.

📌 Key moments:
00:00 – Introduction to SDC Generation in SOC Canvas
00:16 – Seamless Rendering: From CMU to SDC Diagram
00:28 – Automating Tcl Generation via Clock Declaration Points
00:45 – Specifying Hierarchy Paths for PLLs and Clock Sources
01:04 – Managing Clock Groups: Defining Synchronous vs. Asynchronous Relations
01:22 – Collaborative Workflow: Solving Data Consistency for RTL & Physical Engineers
01:43 – Real-time Sync Demo: Automatic SDC Updates upon CMU Design Changes