🎞️ Define Hard IP boundary
SoCCanvasFirstDemo – Hard IP Modeling (Preparation)
코드없는 SoC 설계,
그 시작은 Hard IP를 정의하는 것에서 출발합니다.
🧭 How to design SoC with SoC Canvas
Episode 1에서는
SoC Canvas 를 사용하여 Clock, Power, DFT 설계를 위해서 필요한
Hard IP와 Generic Cell의 Modeling 과정을 보여드립니다.
SoC Canvas는 이 Modeling을
직관적인 GUI 환경에서 일관되게 관리할 수 있도록 지원합니다. 🎬
이번 영상에서는
Hard IP Modeling을 시작하기 전 필요한 준비 과정을 확인하실 수 있습니다.
🎥 Episode 1: Hard IP Modeling (Preparation)
▶️ 전체 데모 영상이 궁금하신 분들은 댓글이나 DM 주시면 링크를 공유드리겠습니다.
SoCCanvasFirstDemo – Hard IP Modeling (Preparation)
Code-free SoC design,
begins with defining the Hard IP.
🧭How to design SoC with SoC Canvas
In Episode 1,
we demonstrate the modeling process for the Hard IP and Generic Cells
required for Clock, Power, and DFT design using SoC Canvas.
SoC Canvas supports consistent management of this modeling within an intuitive GUI environment. 🎬
In this video,
you can check the preparation steps necessary before starting Hard IP modeling.
🎥 Episode 1: Hard IP Modeling (Preparation)
▶️ If you are interested in the full demo video, please leave a comment or send a DM, and we will share the link.
💡 Summary
Before starting the actual design, it needs to define:
⦁ PLL control signals and Frequency Calculation Spec.
⦁ Generic Cell Information.
⦁ Hard IP boundary information
⦁ Hard IP VDD/VSS information
📌 Key moments:
00:00 – Introduction to Hard IP Modeling Preparation
00:13 – PLL Modeling: Defining Control Signals & Formulas
01:30 – Configuring Clock Components (MUX & Dividers)
02:02 – Removing Process Dependency with Generic Definitions
03:38 – UPF Setup: VDD, Ground, and Voltage Information
04:32 – DFT & HMIF: Defining Hard Macro Boundary Info
05:02 – PAD Control Information for GPIO Controllers