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Power System IP for SOC System Design

Overview

Power Canvas is No-code based generative System IP 
that supports Full-Custom SOC Power System

Power Canvas is a system IP that enables custom design of power control systems within SoCs. As SoCs grow more complex, the cost and time needed to set up power control systems are also increasing.

Additionally, errors from this increased complexity are a major cause of respins and ECOs, which can severely impact project schedules. To solve these challenges, a new design approach is needed.

Key Benefits

Design smarter, consume less

01

Time Saving

Power Canvas allows for the design of power systems for SoCs with dozens of power domains in less than a week using an intuitive GUI. Designs created through the GUI can be generated as RTL output in under 10 minutes.
The output accuracy is guaranteed to be 100% through cross-checking of a precise software framework and hardware model.

02

Leakage Power Reduction

Due to fully hardware level domain-dedicated power control systems, in idle period, leakage power consumption of chip can be reduced up to 90%. Any system domain can have their own power management system. Software is non real time management system, but power canvas enables real time power management and chip can have more chances to save power.

03

Built in DFT

DFT (Design for Test) is challenging because the system engineers and DFT engineers are usually separate. With power canvas, DFT inserted power controllers are automatically generated based on the IEEE 1687 standard. This allows for a true “design for test” approach, where test information is created right from the design stage.

Features

Support for every need in system design

Power control system design without single line of verilog code. You only draw your system in canvas, we can generate function codes. Any combination of systems will operate without errors.

Various power control support

Power gating, retention, state retention power gating can be managed in fully hardware level.

Various system power mode support

Normal, sleep, idle or custom defined system power modes can be configured.

UPF generation

System level and domain level UPF will be generated.

Boot system

Initial boot system with minimum size ROM code. It solves problems of fixed state machine based boot or CPU based boot.

Flexible sequencing

After tape-out, you can change power control sequences, at any time by updating SRAM codes.

Built in DFT

IEEE1687 compatible DFT controlles are inserted in design stage. In test mode, you can have same power controllerbilities.

Built in Debugging

CSR can be uploaded and power canvas will reproduce silicon status in GUI format. It will greatly reduce your debugging time.

Safe system management

ISO26262 certification is in progress, and technically ASIL-D level system management is possible.