DFT/IO System IP for SOC System Design
Overview
DFT Canvas is No-code based generative System IP
that supports Full-Custom SOC DFT/IO System
Traditionally, DFT systems are implemented after logic design is completed, through a separate process. As a result, DFT engineers often lack context about the overall system design, making their work more complex and challenging.
DFT Canvas enables the easy and fast design of DFT IO systems during the logic design stage, significantly improving efficiency and alignment with the system context.
Key Benefits
Faster design, fewer mistakes
01
Time Saving
In conventional flows, testing hard IPs was manual, error-prone, and often delayed until the backend phase. As test complexity grows, these delays can cost weeks in schedule and increase risk.
DFT Canvas enables GUI-based configuration of any hard IP test structure at the RTL stage. Designers can now build a complete and seamless test setup without needing detailed scripting. This not only eliminates late-stage surprises, but also shortens the design cycle significantly.
In many cases, teams report saving over a month in schedule.
Imagine the development cost saved when you reduce a full month from your design process.
02
Flexible IO
Most DFT flows require IO pins to be configured early in the design phase and locked. But in test mode, unexpected bugs often occur due to those rigid IO settings.
DFT Canvas supports fully configurable IO logic even during test mode, allowing teams to avoid the typical bring-up issues tied to test pin behavior.
You no longer need to rework IO or re-spin designs just to fix test signal routing. This flexibility ensures smoother chip bring-up and fewer debug headaches. It’s a simple solution to a costly and common DFT problem.
03
DFT Network
DFT Canvas provides a fully GUI-driven environment for creating complex IEEE 1687 (IJTAG) networks. It supports integration with conventional tools like Synopsys TestMax or Cadence Modus.
The user can easily define DFT scan chains, access networks, and hierarchy without low-level scripts. This eliminates the risk of manual error and reduces dependency on DFT experts.
Even non-DFT engineers can configure reliable networks using our intuitive canvas interface.
The result is faster test architecture development with fewer bugs and less rework. It brings both productivity and confidence to DFT integration.
Features
Support for every need in system design
Hard IP and IO design without single line of verilog code. You only draw your system in canvas, we can generate function codes. Any combination of systems will operate without errors.