Clock System IP for SOC System Design
Overview
Clock Canvas is No-code based generative System IP
that supports Full-Custom SOC Clock System
As SoCs grow more complex, the cost and time needed to set up clock control systems are also increasing.
Additionally, errors from this increased complexity are a major cause of respins and ECOs, which can severely impact project schedules. To solve these challenges, a new design approach is needed.
Key Benefits
Design smarter, consume less
01
Time Saving
Clock Canvas allows for the design of clock systems for SoCs with dozens of clock domains in less than a week using an intuitive GUI. Designs created through the GUI can be generated as RTL output in under 10 minutes.
The output accuracy is guaranteed to be 100% through cross-checking of a precise software framework and hardware model.
02
Dynamic Power Reduction
Due to fully hardware level clock control systems, in short idle period, dynamic power consumption of chip can be completely removed. Mordern hyper scale SOC has more than few thousands of clock gating nodes, and they cannot be properly controlled by software. Clock canvas enables ultra fine grain clock gating and system management.
03
Built in DFT
DFT (Design for Test) is challenging because the system engineers and DFT engineers are usually separate. With Clock Canvas, DFT inserted clock controllers and OCC insertion points for DFT are automatically generated based on the IEEE 1687 standard.
This allows for a true “design for test” approach, where test information is created right from the design stage.
Features
No code based system design
Clock control system design without single line of verilog code. You only draw your system in canvas, we can generate function codes. Any combination of systems will operate without errors.